The present invention relates generally to testing compression techniques as applied to semiconductor logic circuitry, and, more particularly, to a method for blocking unknown values in output response of scan test patterns for testing circuits.
Continuous scaling of semiconductor technology has increased IC chip complexity. As the design complexity increases, test data volume also increases rapidly. Since test data volume is a major factor that determines test cost, several test compression techniques including commercial tools to reduce both volume of input test patterns and output responses have been developed. Spatial compaction reduces response data volume by reducing the number of outputs (typically outputs of scan chains) that are observed by the automatic test equipment (ATE). Another approach, temporal compaction, reduces response data volume by compressing a long sequence of responses into a single signature, which is smaller than the size of even a single output response. Hence using a temporal compactor such as multiple input signature register (MISR) can drastically reduce response data volume.
The presence of unknown values (unknowns for short) in output responses of scan test patterns creates a lot of complications for test data compression. Especially, entrance of any unknown into a temporal compactor can be catastrophic since it corrupts the signature of output responses over the entire period of testing time. Unknowns can occur due to the presence of non-scan flip-flops, embedded memories, or tristate buffers. Limitation in accuracy of simulation can also produce unknowns. To prevent corrupting the signature, every unknown that appears at outputs must be blocked before it enters the temporal compactor. Techniques to block unknowns for temporal compaction have been proposed. Since blocking unknowns for temporal compaction requires control data that also contribute to overall test data volume, it is important to reduce control data volume.
A selective compactor scheme where only one scan chain output is observed (not blocked) at any scan shift cycle has been proposed. The selective enhanced selective compactor proposed can observe multiple scan chains at a scan shift cycle at the expense of higher area overhead and larger control data volume. The simple channel masking technique is commonly used in Logic Built-in Self-Test (LBIST). In this scheme, fault effects that are scanned out at scan shift cycles when all scan chains are blocked cannot be observed. An enhanced channel masking scheme presented improves observability of the simple channel masking scheme.
One unknown blocking scheme is based on LFSR reseeding for LBIST. In order to reduce the number of seeds that are stored in an on-chip memory, a best feedback polynomial of LFSR is searched from a set of different degrees of polynomials. The critical drawback of this method is its prohibitive run time. It has been shown that run time for computing control data and control data sizes can be significantly reduced by using an efficient process. Another unknown masking technique proposed uses a combinational logic called XML to generate blocking control signals. Since the process used to minimize hardware overhead for the XML is based on traversing the large fault isolation table, the main drawback of this method is its huge memory space requirement. Since the hardware (XML) for this method is customized for a specific set of test responses, the whole XML should be redesigned for any design change.
All unknown blocking schemes introduced above block not only unknowns but also errors (fault effects) for modeled and unmodeled faults. With one unknown blocking scheme based on LFSR reseeding, the signal probability of every output of an LFSR is 0.5. In other words, if a long sequence of control patterns is generated, the output of every LFSR stage will be set to 1 (0) in 50% of clock cycles. Hence, 50% response data that are scanned out of outputs of scan chains will be blocked, i.e., not be observed. Not observing some scan cells can result in decrease in modeled and/or unmodeled fault coverage.
A large IC chip is comprised of several sub-blocks. Sources of unknowns are typically located in only a few sub-blocks. For example, if a sub-block requires very tight timing, some flip-flops in the sub-block are not scanned so that they function as unknown sources during scan based testing. Each scan chain is usually routed with flip-flops in the same sub-block since mixing flip-flops in different sub-blocks together into one scan chain makes diagnosis difficult. Hence typically most unknowns are captured in scan chains for a few sub-blocks.
Accordingly, there is a need for a new unknown blocking scheme based on LFSR reseeding that can minimize control data volume and maximize the number of scan cells that are observed, especially for designs where unknowns concentrate in a part of the design.